library verilog;
use verilog.vl_types.all;
entity zet_cache_line is
    port(
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        wb_data         : in     vl_logic_vector(15 downto 0);
        shift           : in     vl_logic_vector(4 downto 0);
        we_data         : in     vl_logic;
        we_shift        : in     vl_logic;
        cache_not_full  : out    vl_logic;
        bytes_in_cache_line: out    vl_logic_vector(4 downto 0);
        cache_line      : out    vl_logic_vector(127 downto 0)
    );
end zet_cache_line;
